1. Field of the Invention
The present invention relates to a multi-stage Successive Approximation Register Analog-to-Digital Converter (SAR ADC) and an analog-to-digital converting method using the same, and more particularly, to a multi-stage SAR ADC capable of increasing an analog-to-digital conversion rate by connecting SAR ADCs in multiple stages and an analog-to-digital converting method using the same.
2. Discussion of Related Art
In general, a SAR ADC is an ADC having a structure in which a single comparator is repeatedly used. The SAR ADC has a simple circuit without an analog circuit using an amplifier like a Sampling/Holding Amplifier (SHA), thereby minimizing an area and power consumption. The SAR ADC is easily applicable to a low-voltage circuit. However, since the SAR ADC repeatedly uses the same circuit, there is a problem in that an operating rate is limited to several tens of MHz. Accordingly, a conventional high-speed and high-resolution ADC is usually implemented using a pipeline ADC.
FIG. 1 schematically shows a structure of a conventional pipeline ADC.
Referring to FIG. 1, the conventional pipeline ADC includes a SHA 110 for sampling and holding a first analog input voltage Vin, a plurality of sub-ranging ADCs 120a and 120b, a flash ADC 130, and a digital compensation circuit 140.
In the conventional pipeline ADC, the sub-ranging ADCs 120a and 120b sequentially perform digital conversion of the analog input voltage Vin and the flash ADC 130 performs digital conversion for a Least Significant Bit (LSB). Accordingly, target digital conversion resolution of the analog input voltage Vin is a sum of digital conversion resolutions of the sub-ranging ADCs 120a and 120b and the flash ADC 130.
Here, a detailed structure of each of the sub-ranging ADCs 120a and 120b includes a flash ADC 129 and a Multiplying Digital-to-Analog Converter (MDAC) configured with a SHA 121, an adder 123, an amplifier 125, and a DAC 127.
Operation of the sub-ranging ADCs 120a and 120b will be described. When an analog signal is input from a front stage, the flash ADC 129 digitally converts a partial signal and the DAC 127 converts the digitally converted partial signal into an analog signal. Then, the adder 123 adds a sampled analog signal from the SHA 121 to the analog signal from the DAC 127. The amplifier 125 amplifies and outputs a signal from the adder 123 to the next stage.
As described above, the pipeline ADC is configured with the sub-ranging ADCs 120a and 120b for digitally converting a portion of an input signal. Accordingly, the ADC may perform relatively high-speed and high-resolution analog-to-digital conversion.
However, the SHA 121 included in each of the sub-ranging ADCs 120a and 120b is configured with one amplifier and multiple capacitors. As the operating rate and resolution of the ADC increase, an amount of current to be consumed increases due to a Direct Current (DC) gain limit and bandwidth of the amplifier. Since the SHA 121 is placed in an input stage, noise and non-linear characteristics of the capacitor and amplifier affect the entire ADC, resulting in degradation of performance. In addition, since the number of comparators to be used in the flash ADC 129 increases to a power of 2 according to required resolution, a chip size significantly increases when an at least 4-bit flash ADC is used.